The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor component arranged in a semiconductor body according to the principle of charge carrier compensation. The semiconductor component has a semiconductor basic body arranged in the semiconductor body and at least one semiconductor layer arranged in the semiconductor body and adjoining the semiconductor basic body at the boundary layer. The basic body has at least one compensation layer which adjoins the boundary layer and it has first regions of the first conductivity type and second regions of the second conductivity type, which form a grid in the layout. A total quantity of charge of the first regions corresponds approximately to a total quantity of charge of the second regions. The semiconductor layer adjoins the semiconductor basic body at the boundary layer. A multiplicity of doped regions are embedded in the first surface of the semiconductor layer, the doped regions form a grid for a cell array of the semiconductor component.
Furthermore, the invention relates to two methods of fabricating such a semiconductor component.
The invention thus generally relates to semiconductor components according to the principle of charge carrier compensation and, in particular, to the fabrication of such so-called compensation components. The construction and the method of operation of compensation components is known in many cases and described for example in the U.S. Pat. Nos. 5,216,275 and 4,754,310, and also in international PCT publication WO 97/29518 and in German patent DE 43 09 764 C2.
Compensation components are expected in the near future to take a very large market share in particular in the segment of MOS semiconductor components having a high blocking capability; at the present time, the fabrication of such compensation components is still extremely complicated and time-consuming. This can be attributed firstly to the fact that, in contrast to conventional semiconductor components, the structure of a compensation component to be produced is already inherent in the semiconductor body during provision and processing and, therefore, has to be concomitantly taken into account. This means, for example, that in the case of a power MOSFET which is designed as a compensation component and is designed to take up a reverse voltage of 600 volts, for example, a series of five to seven alternating epitaxy and doping steps have to be performed in the construction technique preferably used hitherto. However, the fabrication of a compensation component using epitaxy and doping steps that have to be employed in such an alternating fashion requires a very long time for processing the basic material. A processed basic body is then obtained which, in the region of the active cell array, that is to say below the gate electrode, is prepared in a desired manner.
Furthermore, in conventional compensation components, the cell grid is typically not homogeneous: the cell grid is many times larger in the active region of the cell array than in the edge region, with the result that the edge region and the active region have to be fabricated separately during processing, which is very complicated.
Compared with conventional semiconductor components, which have a homogeneous inner zone grown epitaxially, for example, compensation components have alternating layers of the first and second conductivity types in the grown epitaxial layer. The main difficulty in fabricating compensation components consists in aligning these alternating layers with regard to the grid of the cell array, that is to say they are arranged in a pillar-shaped, v-shaped, u-shaped or similar manner either below the active cell and/or arranged below the gate electrode.
This requirement for aligning the regions of the first and second conductivity types that are introduced into the semiconductor body in a pillar-like manner with the structures of the active cell array makes the entire fabrication process complicated, lengthy and costly.
A further disadvantage of such compensation components is that, for virtually every different cell design, a process for producing the compensation structures which is tailored to the corresponding component in a dedicated manner has to be provided in each case, which process cannot, however, be applied to compensation components having a different cell design. It is thus virtually impossible to decouple the fabrication of the semiconductor basic body and the corresponding cell array. Therefore, for the multiplicity of semiconductor components the corresponding semiconductor basic bodies cannot be preprocessed, which, moreover, also renders the entire fabrication of such compensation components unnecessarily expensive. Furthermore, since in conventional compensation components the actual process for fabricating the transistor structures and the process for fabricating the compensated xe2x80x9cstarting materialxe2x80x9d are coupled to one another, these processes cannot be optimized separately.
It is accordingly an object of the invention to provide a semiconductor compensation component and a corresponding production method, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which compensation components can be fabricated with the least possible degree of complexity and thus cost-effectively. Furthermore, the invention is based on the object of decoupling, in particular, the process for fabricating the basic material of compensation components from the actual processing of the cell structures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component, comprising:
a semiconductor basic body disposed in a semiconductor body;
said basic body having a compensation layer adjoining a boundary and containing a grid layout of first regions of a first conductivity type and second regions of a second conductivity type, wherein a total quantity of charge of said first regions substantially corresponds to the total quantity of charge of the second regions;
a semiconductor layer disposed in the semiconductor body and adjoining said semiconductor basic body at said boundary;
said semiconductor layer having a first surface with a multiplicity of doped regions embedded therein defining a grid for a cell array of the semiconductor component; and
wherein an alignment of said grid layout of said first and second regions is independent of said grid for the cell array in said semiconductor layer.
In other words, a semiconductor component arranged in a semiconductor body according to the principle of charge carrier compensation is provided,
having a semiconductor basic body arranged in the semiconductor body, which basic body has at least one compensation layer which adjoins a boundary layer and wherein first regions of the first conductivity type and second regions of the second conductivity type are provided, which form a grid in the layout, the total quantity of charge of the first regions approximately corresponding to the total quantity of charge of the second regions,
having at least one semiconductor layer arranged in the semiconductor body and adjoining the semiconductor basic body at the boundary layer, in the first surface of which semiconductor layer a multiplicity of doped regions are embedded, which form a grid for a cell array of the semiconductor component, wherein the grid in the semiconductor layer is not aligned with the grid of the semiconductor basic body.
With the above and other objects in view there are furthermore provided two methods for fabricating the component:
Accordingly, provision is made of a method for fabricating a semiconductor component according to the principle of charge carrier compensation, having the following method steps that are carried out one after the other:
a) a semiconductor body is provided;
b) a compensation layer containing doped regions of the first and/or of the second conductivity type is produced in the semiconductor body;
c) a semiconductor layer is applied to the compensation layer;
d) the doped regions for structures of a cell array and of an edge region of a semiconductor component are embedded in the semiconductor layer, the structures of the doped regions not being aligned with a grid of the structures of the compensation layer that are formed by the regions.
In an alternative method, the following method steps are carried out one after the other:
a) a semiconductor body is provided,
b) at a first surface, the doped regions for structures of a cell array and of an edge region of a semiconductor component are embedded in the semiconductor layer;
c) a compensation layer containing doped regions of the first and/or of the second conductivity type is produced by means of a second surface, the structures of the compensation layer not being aligned with a grid of the structures formed by the doped regions of the cell array.
The particular advantage of the present invention is that the fabrication processes for providing a semiconductor basic body can be completely decoupled from the corresponding processes for fabricating the actual structures of the semiconductor component. The new concept here is that only compensated xe2x80x9csubstrate materialxe2x80x9d is fabricated, in the case of which the corresponding compensation structures are formed according to the desired dielectric strength and current-carrying capacity of the semiconductor component and which has the corresponding thickness for this. An appropriate semiconductor layer is then applied to this substrate material and only then is the actual process for fabricating the cell structures of the semiconductor component carried out. This substrate material may be prefabricated depending on producibility possibilities and need not be aligned with the actual cell structures of the subsequently applied epitaxial layer on the front side of the wafer. Thus, the present invention presents virtually a modular principle for the further development of compensation components, with the fundamentally new idea of separating the production and optimization of basic material and cell array not aligned therewith.
In compensation components of the generic type, the p-doped pillars are in each case arranged exactly below the body zones and/or below the gate electrodes. In a total departure from the construction of compensation components according to the prior art, the requirement for alignment is obviated in the case of the invention""s arrangement of a compensation component.
The compensation structure may, on the one hand, completely occupy the semiconductor basic body. Here, it is typically, but not necessarily, the case that a contact implantation is performed at the rear side of the wafer, which ensures an improvement in the electrical contact to the corresponding rear side electrode. On the other hand, the compensation layer may occupy merely a part of the basic body. The respective other part typically has a higher doping concentration than the compensation layer.
The doping regions of the first and second conductivity types within the compensation layer advantageously extend vertically over the entire thickness of said compensation layer. In a special refinement, these doping regions can be connected to the rear side of the wafer.
In accordance with another feature of the invention, the doping regions of the compensation layer have a fixed spacing relative to one another laterally and extend over the entire width of the compensation layer.
The cell geometry or the grid of the semiconductor layer and also of the compensation layer can have a more or less arbitrary layout. However, it is recommended that structures be used wherein the grid in the cell geometry of the semiconductor layer and in the compensation layer match one another. However, this is not absolutely necessary. Rather, the grid of the cells in the semiconductor layer can differ from the grid in the compensation layer.
Particular advantage is attached to a hexagonal grid, which has the densest packing in terms of area. Further advantageous layouts emerge in the case of a strip-shaped, rectangular or meandering layout. However, round or oval or similar cell structures would also be advantageous.
Furthermore, it is particularly advantageous if the grid of the semiconductor layer is at least partly narrower than the grid in the compensation layer. As an alternative, it may also be provided that the grid of the semiconductor layer is situated more or less perpendicularly on the grid of the compensation layer in plan view. This is particularly advantageous in particular in the case of rectangular or strip-shaped layouts.
Typically, the first regions and/or the second regions in the compensation layer are of approximately pillar-shaped or funnel-shaped design, that is to say they taper into the depth of the compensation layer. Furthermore, spherical structures would also be advantageous. These spherical structures need not necessarily be connected to one another, rather it suffices for them to have a spacing in the region of a space charge zone width when a voltage is applied.
For the function of a compensation component, the total quantity of the doping of the first conductivity type and of the second conductivity type in the compensation layer must be approximately identical. This means that the doping concentrations do not differ from one another to an excessively great extent, that is to say by one or more orders of magnitude. For reasons of stability, it is advantageous if the total quantity of charge carriers of the second conductivity type in the compensation layer is slightly greater than the total quantity of charge carriers of the first conductivity type.
The regions of different conductivity types within the compensation layer are typically connected to one another. However, it would also be conceivable for these regions to have a slight spacing in the region of less than or equal to the space charge zone width when a voltage is applied. In this case, undoped or very lightly doped regions may be provided between the first and the second regions.
The invention is particularly advantageously suited to semiconductor components designed as power MOSFETs. A power MOSFET is designed as a semiconductor component which is arranged in a cell array and wherein a multiplicity of individual transistors arranged in a respective cell are provided, which transistors are connected in parallel by their load paths to form a single semiconductor component. Typically, each of these cells in each case has a body zone embedded in the semiconductor layer, wherein body zone, in turn, at least one source zone of the opposite conductivity type is embedded. Furthermore, a power MOSFET has a drain electrode on the rear side of the wafer and, on the front side of the wafer, a source electrode which makes contact with the source zones. Respectively adjacent body zones are spaced apart by an intermediate zone above which a gate electrode insulated by means of a gate oxide is arranged.
The semiconductor layer typically has a basic doping of the first conductivity type. In a special refinement, the semiconductor layer may also have a basic doping of the second conductivity type. In this case, the intermediate zones and the body zones formed from the basic doping of the semiconductor layer extend over the entire thickness of the semiconductor layer and are connected to the compensation layer. Such a design of the semiconductor layer with charge carriers of the second conductivity type is recommended when designing a defined breakdown of the semiconductor component in the breakdown situation, thereby ensuring better stability of the semiconductor component. In a further refinement, the semiconductor layer may also be weakly doped or even undoped. In this case, however, the intermediate zones arranged between the base zones should have a high doping of the first conductivity type.
A semiconductor component of the generic type typically has an active region, which is arranged in a cell array of the semiconductor component, and an edge region as edge termination of the semiconductor component. The particular advantage of the present invention consists, inter alia, also in the fact that the grid may be identical below the cell array and below the edge region. It is not necessary, therefore, to provide a separate process for the regions below the cell array and the edge region, as a result of which the semiconductor components can be fabricated with a lower degree of complexity and thus more cost-effectively.
In a first method according to the invention, for fabricating a compensation component, firstly a semiconductor basic body is provided which has a compensation layer having regions of the first and second conductivity types. A semiconductor layer is subsequently applied on said semiconductor basic body with compensation layer, a multiplicity of doped regions of one and/or the other conductivity type being embedded in the surface of said semiconductor layer. What is essential in this case is that the grid of the doped regions embedded in the semiconductor layer is not aligned with the grid of the compensation layer.
In accordance with a further advantageous method, a semiconductor body is provided in whose first surface doped regions of the first and/or of the second conductivity type are embedded. These doped regions thus form a grid for a cell array of a semiconductor component. Afterward, the semiconductor body is optionally thinned from the opposite, second surface as far as a predetermined thickness. Regions of the first and/or of the second conductivity type are then introduced from the second surface into the semiconductor body in such a way that a compensation layer is formed. These are advantageously not connected to the doped regions at the first surface. What is essential here, too, is that the grid of the compensation layer does not have to be aligned with the grid of the cell array.
A high energy implantation with different energies and doping doses is advantageously performed for the purpose of producing the first and/or the second regions within the compensation layer. An implantation mask fabricated from a thin silicon wafer can advantageously be used for such a high energy implantation. Such an implantation mask has cutouts in the implantation mask at the regions to be doped. The remaining regions of the mask form, during implantation, a perfect screen for the regions that are not to be doped. Moreover, such a mask can be fabricated in a very simple manner.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a compensation semiconductor component and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.